Jorge Iglesias Costas
Jorge Iglesias obtained a Bachelor’s Degree in Electronic Engineering with a Minor in Robotics at La Salle Campus Barcelona - Universitat Ramon Llull (Spain) in 2024. Subsequently, he pursued a Master’s in Microelectronic Design at the Universitat Politècnica de Catalunya - ETSETB (2024–2026), focused on System-On-Chip design and digital nanoelectronics.
He is a Calculus professor and Electronic Engineering tutor at La Salle Campus Barcelona since 2024, having served as a teaching assistant between 2022 and 2024 in subjects such as Analog Electronics, Electronics for Biomedicine, Signal Analysis, Radiofrequency Technologies, and Electronic Measurement Laboratory.
His research includes work as a Research Engineer at the Barcelona Supercomputing Center since 2026, implementing RISC-V processors using open-source EDA flows and performing RTL design, synthesis, and physical analysis of semiconductor systems. Previously, he was a research intern at the Centre Tecnològic de Telecomunicacions de Catalunya (CTTC) between 2023 and 2024, designing a multiband SDR receiver with RFSoC4x2 presented at the NAVITEC ESA Workshop 2024. His projects on memristor-based neural networks and chip solutions for sustainable computing stand out, carried out in collaboration with Esade, UPC, IED, CERN, and the European XFEL.
CV — Jorge Iglesias Costas
Electronic Design Engineer
La Salle Campus Barcelona – Universitat Ramon Llull
Academic Background
• Master’s in Microelectronic Design, Universitat Politècnica de Catalunya - ETSETB (Spain), 2024–2026.
• Bachelor’s Degree in Electronic Engineering, La Salle Campus Barcelona - Universitat Ramon Llull (Spain), 2020–2024.
Teaching Experience
• Calculus Professor and Electronic Engineering Tutor, La Salle Campus Barcelona – Universitat Ramon Llull, 2024–Present.
• Teaching Assistant, La Salle Campus Barcelona – Universitat Ramon Llull, 2022–2024.
Research and Technology Transfer
• Research Engineer, Barcelona Supercomputing Center, 2026–Present; RISC-V processor implementation, RTL design, and physical synthesis.
• Research Intern, CTTC, 2023–2024; design of a multiband SDR receiver with RFSoC4x2.
Additional Information
• Languages: Spanish and Catalan (native), English (advanced)
• Skills: Digital design and nanoelectronics, FPGA/ASIC/SoC/RISC-V, VHDL, Verilog, SystemVerilog, SystemC, RF, electronic instrumentation
• LinkedIn: http://www.linkedin.com/in/jorge-iglesias-costas-b8a4b1295" target="_new" rel="noopener">www.linkedin.com/in/jorge-iglesias-costas-b8a4b1295