Andrés Cardona Cardona

Andrés Cardona Cardona
E-mail
andres.cardona@ext.salle.url.edu
Building
IOTICAT
Address
C. Quatre Camins 30, 08022, Barcelona
Floor
IOT

Academic Education

  • PhD in Electronic and Telecommunication Engineering, Universitat Autònoma de Barcelona (2016).
  • MSc in Micro and Nano Electronics Engineering (specialization in Integrated Electronic Systems), Universitat Autònoma de Barcelona (2009).
  • BSc in Electronics Engineering, Universidad de Antioquia, Medellín (Colombia) (2007).

Teaching Activity

  • PIF Research Fellow at the Universitat Autònoma de Barcelona (2007–2012), teaching courses in digital systems and programming laboratories within the field of electronic engineering and embedded systems.
  • Adjunct Lecturer at La Salle – Universitat Ramon Llull since 2022, teaching in the area of digital electronics (Programmable Integrated Circuits).

Research and Knowledge Transfer Activity

  • His research focuses on the design of FPGA-based digital systems, dynamic partial reconfiguration, fault-tolerant architectures, hardware security, and the hardware implementation of cryptographic algorithms for embedded systems and critical applications.
  • Researcher in the Integrated Systems and Circuits Design (DCSI) group at the Universitat Autònoma de Barcelona, participating in nationally funded research projects, as well as in the European project TOISE (Trusted Computing for European Embedded Systems) at the Institute of Microelectronics of Barcelona (IMB-CNM, CSIC).
  • In the industrial sector, he has worked as a digital and FPGA design engineer in R&D environments, contributing to the development of high-performance real-time electronic systems. He has contributed to the development of FPGA firmware for the magnetic diagnostics control system of the ITER nuclear fusion reactor and to the design of FPGA systems for high-speed data acquisition and processing.
  • He is currently Senior Hardware Design Engineer at Ponos Technology, where he develops and integrates cryptographic hardware blocks in SystemVerilog on high-performance FPGA platforms.

Recognitions

  • PIF Fellowship (Research Training Grant) – Universitat Autònoma de Barcelona (2007).