Andrés Cardona Cardona

Andrés Cardona holds a PhD in Electronic and Telecommunication Engineering from the Universitat Autònoma de Barcelona (2016), where he also completed an MSc in Micro and Nano Electronic Engineering (2009). He obtained his Electronics Engineering degree from the University of Antioquia (2007), later officially recognized in Spain.
His research interests focus on dynamic partial reconfiguration in FPGAs, fault-tolerant architectures, hardware security, and cryptography for critical embedded systems. He is the author of 11 scientific publications in international journals and conferences in the fields of reconfigurable systems, dependability, and secure hardware design.
He has over ten years of experience as a digital and FPGA design engineer in industrial R&D environments. He currently works as a Senior Hardware Design Engineer at Ponos Technology, developing and integrating cryptographic hardware blocks in SystemVerilog on high-performance FPGA platforms. Previously, he contributed to the FPGA firmware development for the ITER nuclear fusion reactor at GTD, and held R&D positions at Keysight Technologies and Recore Systems/Tesorion.